This invent ion relates to a non-volatile semiconductor memory device and a manufacturing method thereof. More particularly, it relates to a non-volatile semiconductor memory device in which a word line is subjected to lining (or backing-up) a wiring as an overlaying layer to reduce the resistance, and a manufacturing method thereof.
Up to now, lining of a word line of a flash memory has been practiced for reducing the resistance of the word line. However, since there was not much demand for high-speed accessing and the first layer wiring, used to be frequently allocated to a bit line, it was sufficient if a word line is connected to the second and following metal wiring layers substantially at a rate of one contact per 512 or 1024 cells so as to be used as lining. However, with the increase in the need for a flash memory embedded in a micro-computer and in the demand for high-speed accessing, it has come up to be felt necessary to raise the lining frequency. FIGS. 5 to 7 show an example of connecting the word line to the metal wiring of the first layer at a rate of one contact per 16 or 32 cells.
FIG. 5 shows an array structure of a flash memory, from its upper surface, after forming a metal wiring of the first layer, and shows two wiring layers 501, 502, with the first wiring layer 501 being the first layer metal wiring serving as a wiring for lining the word line and with the second wiring 502 being a word line of the flash memory, formed of polycide. 503 denotes a contact for electrically connecting the word line 502 to the first layer metal wiring layer 501 for lining. There are provided such contacts 503 at a rate of one contact per 16 or 32 cells. 504 shows an area for a cell of the flash memory A plurality of such cell areas are provided in succession along the word line to provide a spacing for providing a contact per 16 or 32 cells.
FIG. 6 shows a cross-section along a line F-Fxe2x80x2 parallel to the word line of FIG. 5. 601 denotes an isolation oxide film, which is usually a thermal oxide film with a thickness usually as 400 nm. 602 denotes a tunnel oxide film formed by thermal oxidation and is usually of a thickness of the order of 10 nm or less. 603 denotes a floating gate and is formed of polysilicon thinly doped with phosphorus to a thickness of 150 nm. 604 is a film for electrically insulating the floating gate from the control gate. Usually, this film 604 is of a three-layered structure of oxide fiIm/nitrided film/oxide film with a film thickness of 20 nm or less, calculated as an oxide film.
605 is a control gate having a polycide structure formed of polysilicon of an order of 150 nm doped with phosphorus and tungsten silicide of an order of 150 nm. This control gate 605 operates as a word line of the flash memory. 606 denotes a metal wiring layer used for lining the word line and which is usually of a three-layered structure of TiN/AI/TiN. 607 denotes a contact for electrically connecting the word line 605 to the metal wiring layer 606. This contact 607 usually is formed of tungsten.
FIG. 7 shows a cross-sectional view taken along line G-Gxe2x80x2 perpendicular to the word line of FIG. 5, and shows a cross-section of an area where the contact 607 is located. In FIG. 7, the reference numerals used denote the same parts or components as those shown in FIG. 6.
In the course of the investigations toward the present invention, there have been encountered various problems. Namely, the conventional structure has a drawback that it is not possible to increase the read-out speed of the flash memory. The reason is that the contacts used for establishing electrical connection between the word line and the metal wiring layer used for lining are provided only at a rate of one contact for 16 or 32 cells, such that the electrical resistance of the word line cannot be lowered sufficiently. Moreover, if the rate of providing contacts is increased for lowering the resistance, it becomes necessary to provide additional space or spaces for providing the contacts thus leading to the increased memory hip area.
In view of the above-described problems of the prior art, it is a principal object of the present invention to provide a non-volatile semiconductor memory device in which the word line resistance can be lowered without being accompanied by an increased chip area, and a manufacturing method thereof.
For accomplishing the above object, according to an aspect of the present invention there is provided a non-volatile semiconductor memory device having a plurality of memory elements each having a floating gate and a control gate, wherein there is formed, in an inter layer insulating film formed on the control gate, a groove passed through the interlayer insulating film and extending in the direction of a word line, and wherein, by an electrically conductive member embedded in the groove, the control gate is connected to a metal wiring arranged as an overlying layer of the interlayer insulating film.
According to the present invention, the electrically conductive member embedded in the groove may be formed by the same member as the metal wiring arranged as the overlaying layer of the interlayer insulating film.
The present invention also provides a manufacturing method for a non-volatile semiconductor memory device including a plurality of peripheral circuit sections and a plurality of memory elements each having a floating gate and a control gate.
The method comprises at least the steps of (a) forming an inter layer insulating film on the peripheral circuit section and as an overlying layer of the control gate of the memory element, (b) removing a pre-set area of the interlayer insulating film, providing a contact hole in the area of the peripheral circuit section and simultaneously providing a groove extending in the word line direction in a control gate area of the memory element, (c) embedding an electrically conductive member in the contact hole and in the groove, and (d) depositing a metal wiring as an overlying layer of the interlayer insulating film.
The present invention also provides a manufacturing method for a non-volatile semiconductor memory device comprising a plurality of peripheral circuit sections and a plurality of memory elements each having a floating gate and a control gate. This method comprises at least the steps of (a) forming an interlayer insulating film on the peripheral circuit section and as an overlying layer of the control gate of the memory element, (b) removing a pre-set area of the interlayer insulating film, providing a contact hole in an area of the peripheral circuit section and simultaneously providing a groove extending in the word line direction in a control gate area of the memory element, and (c) embedding an electrically conductive member within the contact hole and the groove and simultaneously forming a wiring formed by the same member as the electrically conductive member as an overlying layer of the inter layer insulating film.